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Reset and Reset Configuration
Table 5-1. BCSR/FLASH Hard Reset Configuration Word (continued)
Field
L2CPC
Data
Bus
Bits
8:9
Prog
Value
[Bin]
‘01’
Implication
CI/BADDR(29)/IRQ2 selected as IRQ2
Offset In
Flash
[Hex]
8
Value
[Hex]
72
WT/BADDR(30)/IRQ3 selected as IRQ3
L2_HIT/IRQ4 selected as IRQ4
CPU_BG/BADDR(31)/IRQ5 as IRQ5)
DPPC
10:11
‘11’
Data Parity Pin configuration as:
DP0 as EXT_BR2
DP1 as EXT_BG2
DP2 as EXT_DBG2
DP3 as EXT_BR3
DP4 as EXT_BG3
DP5 as EXT_DBG3
DP6 as IRQ6
DP7 as IRQ7
Reserved
ISB
12
13:15
’0’
’010’
Reserved.
IMMR initial value 0x0F000000, i.e., the
internal space resides initially at this address.
BMS
BBD
16
17
’0’
’0’
Boot memory (Flash) at 0xFE000000.
ABB/IRQ2 pin is ABB
10
36
DBB/IRQ3 pin is DBB
MMR
18:19
’11’
‘11’ - Mask Masters Requests. Boot Master is
MPC8272s 60x.
LBPC
APPC
20:21
22:23
’01’
’10’
‘01’ - Local Bus pins function as PCI bus.
MODCK1/AP(1)/TC(0) functions as BKSEL0
MODCK2/AP(2)/TC(1) functions as BKSEL1
MODCK3/AP(3)/TC(2) functions as BKSEL2
IRQ7~/APE~ functions as IRQ7~
CS11~/AP(0) functions as CS11~
CS10PC
ALD_EN
24:25
26
’01’
’0’
CS10~/BCTL1/DBG_DIS~ functions as BCTL1
PCI Auto Load Enable. When high, PCI Bridge
18
5A
Configuration is done automatically from the
FLASH/E 2 PROM (CPM is configuration master
- PPC core should be disabled) right after the
Hard Configuration Word. When low, the PPC
Core should configure the PCI Bridge.
PCI_MODCK
27
’1’
Determines PCI clock settings as set by
PCI_MODCKH:
‘0’ - PCI clock set by PCI_MODCKH
‘1’ - PCI clock is divided according to
PCI_MODCKH
MODCK_HI 1
28:31
‘1010’
Determines the Core’s frequency out of
power-up reset.
1
Applies only ONCE after power-up reset.
Chapter 5. Module Design
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